Method for simultaneously fabricating capacitor structures, for

Details Method for simultaneously fabricating capacitor structures, for Method for simultaneously fabricating capacitor structures, for

1998-11-02

2000-03-14

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438250, 438393, 438398, 438672, H01L 218242

Patent

active

060372168

ABSTRACT:
A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.

REFERENCES:
patent: 5497017 (1996-03-01), Gonzales
patent: 5635423 (1997-06-01), Huang et al.
patent: 5702990 (1997-12-01), Jost et al.
patent: 5710073 (1998-01-01), Jeng et al.
patent: 5731236 (1998-03-01), Chou et al.
patent: 5879986 (1999-03-01), Sung
S. Nakamura, "A Simple 4 G-bit DRAM Technology Utilizing High-Aspect Ratio Pillars for Cell-Capacitors and Peripheral-Vias Simultaneously Fabricated", 1997 IEEE, IEDM '97, p29-32.

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