Method for manufacturing mixed-mode devices

Details Method for manufacturing mixed-mode devices Method for manufacturing mixed-mode devices

1998-03-17

2000-03-14

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438221, 438275, 438424, 148DIG163, H01L 21336, H01L 218238, H01L 2176

Patent

active

06037201&

ABSTRACT:
A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

REFERENCES:
patent: 4806500 (1989-02-01), Scheibe
patent: 5177028 (1993-01-01), Manning
patent: 5254489 (1993-10-01), Nakata
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5502009 (1996-03-01), Lin
patent: 5895254 (1999-04-01), Huang et al.
Wolf et al, "Silicon Processing for the VLSI Era", vol. 1, pp. 514-517, 1986.

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