Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

Filed on

1998-02-19

Date issued

1999-11-30

Examiner

Hoang, Huan

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Precharge

Other Related Categories

365233, 3652335, G11C 700, G11C 800

Type

Patent

Status

active

Patent number

059954302

Description

ABSTRACT:
An overlaid DQ type DRAM of a clock synchronous type is provided with a column address transition detector circuit, to control pre-charging and equalizing of pairs of DQ lines. An address for selecting a DQ line muptiplexer in a stage prior to a DQ buffer is set to a predetermined column address, and a transition of a column address is detected in a first pipeline stage of a column access path. When only the bit of the predetermined column address changes with the other column address bits kept unchanged, DQ lines are pre-charged and equalized.

REFERENCES:
patent: 5668774 (1997-09-01), Furutani
patent: 5844849 (1998-12-01), Furutani
patent: 5848015 (1998-12-01), Seno

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