Method of fabricating CMOS transistors with a planar shallow tre

Details Method of fabricating CMOS transistors with a planar shallow tre Method of fabricating CMOS transistors with a planar shallow tre

1997-12-31

1999-11-30

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438223, 438224, 438232, H01L 218238

Patent

active

059941782

ABSTRACT:
The present invention discloses a method of forming CMOS transistors with planar shallow trench isolations. Before a twin well being formed, a pad oxide film and a nitride film are sequentially deposited on a silicon substrate. When a photoresist film is patterned to define active regions, the silicon substrate is recessed by using the patterned photoresist film as a mask. A liquid-phase-deposition oxide (LPD) film is then grown on the recess structure for shallow trench isolations. Next, a high temperature annealing procedure is performed to densify the LPD oxide film. Finally, when the pad oxide and the nitride films are removed, processes for fabricating CMOS transistors can be continued on the silicon substrate.

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