Semiconductor memory having an improved reading circuit

Details Semiconductor memory having an improved reading circuit Semiconductor memory having an improved reading circuit

1999-07-16

2000-11-07

Phan, Trong

Static information storage and retrieval

Read/write circuit

Precharge

365205, G11C 700

Patent

active

061446017

ABSTRACT:
A DRAM comprises a first DRAM cell and a second DRAM cell connected to a first bit line and a second bit line, respectively, which constitute a pair of bit lines precharged to a reference potential and which are connected to a sense amplifier for comparing data stored in a memory cell selected from the first and second memory cells with a reference potential, so as to output the result of comparison as a read-out data. When a selected memory cell of the first and second memory cells is read out, a reference potential setting circuit sets the bit line associated to a non-selected memory of the first and second memory cells, to the reference potential at least one time during a period after the one of the first and second memory cells is selected to be read out and before the sense amplifier is activated.

REFERENCES:
patent: 5255223 (1993-10-01), Tanaka
patent: 5748520 (1998-05-01), Asaka et al.
patent: 6018481 (2000-01-01), Shiratake

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