Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-12-14
1998-07-21
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438251, 438199, H01L 218242
Patent
active
057834709
ABSTRACT:
A CMOS DRAM integrated circuit includes paired P-type and N-type wells in a substrate. The wells are fabricated using a self-aligning process. Similarly, FETs of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning process to provide FETs of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. One or more layers having an irregular top surface topology may be planarized using mechanical or chemical-mechanical polishing of the topological layer.
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LSI Logic Corporation
Tsai Jey
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