Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1999-03-23
2000-11-07
Tran, Andrew Q.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257322, 257324, 257326, 257314, 257315, 438262, 438263, 438264, 438297, H01L 29788
Patent
active
061440647
ABSTRACT:
Methods of forming EEPROM memory cells having uniformly thick tunneling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG.. To prevent unwanted growth of the tunneling oxide layer, a silicon nitride layer is preferably patterned on the tunneling oxide layer and used as an oxidation mask during the step of growing the preliminary field oxide isolation region to a second thickness. The silicon nitride mask is then removed and then a floating gate electrode and insulated control electrode are patterned on the tunneling oxide layer and channel region to complete the memory cell.
REFERENCES:
patent: 5110756 (1992-05-01), Gregor et al.
patent: 5147813 (1992-09-01), Woo
patent: 5286666 (1994-02-01), Katto et al.
patent: 5385856 (1995-01-01), Hong
patent: 5479036 (1995-12-01), Hong
patent: 5521109 (1996-05-01), Hsue et al.
patent: 5663080 (1997-09-01), Cereda et al.
patent: 5888871 (1999-03-01), Cho et al.
Cho Myoung-kwan
Kim Keon-soo
Samsung Electronics Co,. Ltd.
Tran Andrew Q.
LandOfFree
Split-gate EEPROM device having floating gate with double polysi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Split-gate EEPROM device having floating gate with double polysi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Split-gate EEPROM device having floating gate with double polysi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1643848