Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-11-29
1998-09-22
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, 438396, 438397, 148DIG14, H01L 218242
Patent
active
058113320
ABSTRACT:
Fabricating a semiconductor memory device on a substrate having a transfer transistor formed thereon includes forming a first insulating layer over the transfer transistor, an etching protection layer over the first insulating layer, a second insulating layer over the etching protection layer, and a stacked layer over the second insulating layer, wherein the stacked layer has a recess therein disposed above a source/drain region of the transistor and exposing a portion of the second insulating layer. A third insulating layer is formed around the periphery of the recess and a fourth insulating layer is formed to fill the recess. Then the process includes removing the third insulating layer and the fourth insulating layer from the recess, and a portion of the second insulating layer directly below the third insulating layer to form a cavity which does not expose the etching protection layer. A first conductive layer is then formed to fill the recess and the cavity, followed by removing the stacked layer. A fifth insulating layer is formed above the second insulating layer and the first conductive layer and a second conductive layer is formed over the fifth insulating layer, the second conductive layer penetrating the fifth insulating layer, the first conductive layer, the second insulating layer, the etching protection layer, and the first insulating layer, and being in electrical contact with the source/drain region. The second and fifth insulating layers are removed and a dielectric layer, a third conductive layer are formed on exposed surfaces of at least the first and second conductive layers.
REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5089869 (1992-02-01), Matsuo et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5126810 (1992-06-01), Gotou
patent: 5142639 (1992-08-01), Kohyama et al.
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5158905 (1992-10-01), Ahn
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5172201 (1992-12-01), Suiza
patent: 5196365 (1993-03-01), Gotou
patent: 5206787 (1993-04-01), Fujioka
patent: 5266512 (1993-11-01), Kirsch
patent: 5274258 (1993-12-01), Ahn
patent: 5338955 (1994-08-01), Tamura et al.
patent: 5354704 (1994-10-01), Yang et al.
patent: 5371701 (1994-12-01), Lee et al.
patent: 5389568 (1995-02-01), Yun
patent: 5399518 (1995-03-01), Sim et al.
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5443993 (1995-08-01), Park et al.
patent: 5453633 (1995-09-01), Yun
patent: 5478770 (1995-12-01), Kim
patent: 5508222 (1996-04-01), Sakao
patent: 5521419 (1996-05-01), Wakamiya et al.
patent: 5523542 (1996-06-01), Chen et al.
patent: 5550080 (1996-08-01), Kim
patent: 5561309 (1996-10-01), Cho et al.
patent: 5561310 (1996-10-01), Woo et al.
patent: 5572053 (1996-11-01), Ema
patent: 5595931 (1997-01-01), Kim
patent: 5721168 (1998-02-01), Wu
"Mini-Trenches in Polysilicon For Dram Storage Capacitance Enhancement", IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", International Electron Devices Meeting, pp. 592-595, Dec. 1988.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical papers. pp. 69-70.
Nguyen Tuan H.
United Microeletronics Corp.
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