Silicon on insulator (SOI) dram cell structure and process

Details Silicon on insulator (SOI) dram cell structure and process Silicon on insulator (SOI) dram cell structure and process

Filed on

1996-10-22

Date issued

1998-09-22

Examiner

Chaudhari, Chandra

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

438155, H01L 218242

Type

Patent

Status

active

Patent number

058112839

Description

ABSTRACT:
A silicon on insulator (SOI) DRAM has a layer of buried oxide covered by a thin layer of crystalline silicon on the surface of a bulk silicon substrate. Field oxide regions are formed extending through the thin crystalline silicon surface layer and into contact with the buried oxide layer. Gate oxide layers, gate electrodes and source/drain regions for the transfer FETs of the DRAM are formed in and on the thin crystalline silicon surface layer in the active regions between the field oxide regions. A trench is opened through one of the source/drain regions of each of the transfer FETs. A layer of doped polysilicon is provided to line the trenches and is patterned to form at least a part of the bottom electrodes of the charge storage capacitors for the DRAM. The bottom electrodes are covered with a thin dielectric layer and an upper electrode of doped polysilicon is provided. Preferably, the trench for the bottom capacitor electrode extends through the buried oxide layer and may extend into the bulk silicon.

REFERENCES:
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5504027 (1996-04-01), Jeong et al.
patent: 5618745 (1997-04-01), Kita
Fan, J., "New Anatomies for Semiconductor Wafers," IEEE Spectrum, Apr. 1989, pp. 34-38.
Kim, H. et al., "A High Performance 16M DRAM on a Thin Film SOI," 1995 Symposium on VLSI Technology Digest of Technical Papers, Apr. 1995, pp. 143-144.
Wolf, "Silicon Processing for the VLSI Era, vol. 2: Process Integration," pp. 68-78 (1990).

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