Method for manufacturing an MOS transistor having a self-aligned

Details Method for manufacturing an MOS transistor having a self-aligned Method for manufacturing an MOS transistor having a self-aligned

1997-07-07

1998-10-27

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438692, 438564, H01L 21336

Patent

active

058277684

ABSTRACT:
A new method for manufacturing an MOS transistor is applied in the deep submicron process. In this method, a polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process. This method can reduce short channel effects and the series impedance of the source/drain as well as accomplish the local interconnection of a circuit and planarization. Therefore, this method is very suitable for manufacturing devices in the deep submicron process.

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