Semiconductor memory device synchronous with external clock sign

Details Semiconductor memory device synchronous with external clock sign Semiconductor memory device synchronous with external clock sign

1997-06-20

1998-10-27

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523006, 36523008, 365233, G11C 800

Patent

active

RE0359343

ABSTRACT:
A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal, and a column addressing system incorporated in the synchronous dynamic random access memory device forms a plurlaity of pipeline stages together with an input/output unit for sequentially supplying data bits to a data port in response to a column address internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus.

REFERENCES:
patent: 4856106 (1989-08-01), Teraoka
patent: 5047984 (1991-09-01), Monden
patent: 5341341 (1994-08-01), Fukuzo

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