Static information storage and retrieval – Read/write circuit – Precharge
Patent
1988-06-27
1990-08-28
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Precharge
365222, 365194, 3652335, 307279, G11C 700, G11C 1140
Patent
active
049531301
ABSTRACT:
A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.
REFERENCES:
patent: 4421996 (1983-12-01), Chuang et al.
patent: 4641049 (1987-02-01), Fukuzo
patent: 4689771 (1987-08-01), Wang et al.
patent: 4751680 (1988-06-01), Wang et al.
patent: 4764900 (1988-08-01), Bader et al.
patent: 4779228 (1988-10-01), Uchiyama et al.
patent: 4800304 (1989-01-01), Takeuchi
patent: 4811290 (1989-03-01), Watanabe
patent: 4813021 (1989-03-01), Kai et al.
patent: 4820942 (1989-04-01), Chan
Braden Stanton C.
Comfort James T.
Garcia Alfonso
Hecker Stuart N.
Sharp Melvin
LandOfFree
Memory circuit with extended valid data output time does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory circuit with extended valid data output time, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit with extended valid data output time will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1594799