Method of forming trench transistor in combination with trench a

Details Method of forming trench transistor in combination with trench a Method of forming trench transistor in combination with trench a

1998-02-24

2000-05-02

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, 438272, 438300, H01L 2176

Patent

active

060571942

ABSTRACT:
An IGFET in combination with a trench array is disclosed. A semiconductor substrate includes first and second x-direction trenches and first, second and third y-direction trenches generally orthogonal to intersecting with the x-direction trenches. The x-direction trenches and the first and second y-direction trenches surround a first generally rectangular region of the substrate, the x-direction trenches and the second and third y-direction trenches surround a second generally rectangular region of the substrate, and the second y-direction trench is between the first and second substrate regions. A gate insulator is on a bottom surface of the second y-direction trench, and insulative spacers are adjacent to opposing sidewalls of the second y-direction trench. A gate electrode is on the gate insulator and the spacers, in the y-direction trench, and electrically isolated from the substrate. A source is in the first substrate region and beneath and adjacent to the bottom surface of the second y-direction trench, and a drain is in the second substrate region and beneath and adjacent to the bottom surface of the second y-direction trench. The x-direction trenches and the first and third y-direction trenches are filled with an insulator and provide device isolation for the IGFET. Advantageously, all the trenches are formed simultaneously using a single etch step.

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