Semiconductor memory device having high-speed three-state data o

Details Semiconductor memory device having high-speed three-state data o Semiconductor memory device having high-speed three-state data o

1992-04-13

1994-03-15

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365168, 36518908, 3652335, G11C 700, G11C 800

Patent

active

052950980

ABSTRACT:
A dynamic random access memory device is equipped with an output data buffer circuit for driving an output data pin, and the output data buffer circuit comprises an output inverter coupled with the data pin, a driving unit responsive to a data bit on a data line pair in the absence of a high-impedance control signal for controlling the output inverter, the driving unit being further operative to cause the output inverter to enter high-impedance state in the presence of the high-impedance control signal, and a switching transistor coupled between the data pin and a constant voltage source and responsive to a preceding signal for coupling the output data pin with the constant voltage source, wherein the high-impedance control signal and the preceding signal are supplied to the output data buffer circuit before reaching the data bit thereto so that power voltage lines are prevented from voltage fluctuation without sacrifice of switching speed.

REFERENCES:
patent: 4604731 (1986-08-01), Konishi
patent: 4858197 (1989-08-01), Aono et al.
patent: 4879693 (1989-11-01), Ferrant
patent: 4953130 (1990-08-01), Houston
patent: 5060196 (1991-10-01), Pae et al.

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