Low power precharge circuit for a dynamic random access memory

Details Low power precharge circuit for a dynamic random access memory Low power precharge circuit for a dynamic random access memory

1996-12-17

1998-04-28

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365205, 365207, G11C 700

Patent

active

057454230

ABSTRACT:
A low power precharge circuit for a dynamic random access memory (DRAM) is disclosed. The present invention includes an equalization circuit connected to a pair of bitlines for allowing electric charge of the bitline having higher voltage to flow to the bitline having lower voltage after being activated by a precharge control signal. A voltage pull circuit is used to provide a constant voltage in response to a first sense control signal. Further, a voltage amplifying circuit connected to the pair of bitlines is used to amplify the voltages of the bitlines in response to a second sense control signal so that the voltage of one bitline is complementary to the voltage of the other bitline.

REFERENCES:
patent: 5426603 (1995-06-01), Nakamura et al.
patent: 5463584 (1995-10-01), Hoshino
patent: 5544110 (1996-08-01), Yuh
patent: 5646880 (1997-07-01), Yuh

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