Compensation technique for parasitic capacitance

Details Compensation technique for parasitic capacitance Compensation technique for parasitic capacitance

1997-03-21

1998-04-28

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438250, 438251, H01L 2702

Patent

active

057443858

ABSTRACT:
Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.

REFERENCES:
patent: 5006733 (1991-04-01), Brown
patent: 5021681 (1991-06-01), Colbeck et al.
patent: 5063309 (1991-11-01), Yamasaki
patent: 5173835 (1992-12-01), Cornett et al.
patent: 5281931 (1994-01-01), Bailey et al.
patent: 5356826 (1994-10-01), Natsume
patent: 5500387 (1996-03-01), Tung et al.
patent: 5530399 (1996-06-01), Chambers et al.

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