Multiple input two-level cache directory with mini-directory for

Details Multiple input two-level cache directory with mini-directory for Multiple input two-level cache directory with mini-directory for

1997-04-09

1999-01-12

Lane, Jack A.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711122, 711131, G06F 1208

Patent

active

058600787

ABSTRACT:
A method and apparatus for implementing a fully associative cache directory that stores X cache tags and responds to N read cache tags simultaneously in a single cache directory access to provide a corresponding cache block index for each of the N read cache tags. The cache directory includes a mini-directory and a main directory. The mini-directory stores M cache tags and corresponding block indexes, wherein M is equal to at least N. The mini-directory is fully associative and simultaneously compares each of the M stored cache tags against each of the N read cache tags. The main directory stores the X cache tags and provides corresponding block indexes. The main directory is fully associative and compares P read cache tags against each of the X cache tags simultaneously, P being less than N. The N read cache tags are initially compared against the mini-directory to provide a block index for each of the N read cache tags that hits in the mini-directory. Only those read cache tags that miss in the mini-directory are compared against the main directory.

REFERENCES:
patent: 5249282 (1993-09-01), Segers
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5307477 (1994-04-01), Taylor et al.
Khan, Ashis, "CMOS and ECL implementation of MIPS RISC architecture", Microprocessors and Microsystems, 14 (1990) Jul./Aug., No. 6, London, GB.

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