Method of forming a DRAM stacked capacitor using an etch blockin

Details Method of forming a DRAM stacked capacitor using an etch blockin Method of forming a DRAM stacked capacitor using an etch blockin

1997-07-07

1999-09-14

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 18242

Patent

active

059536080

ABSTRACT:
A method of forming a stacked capacitor of a dynamic random access memory is disclose. The stacked capacitor is provided on a transistor and comprises first and second electrodes and a dielectric film sandwiched therebetween. The first electrode serving as a storage node. A first silicon oxide film is deposited on an interlayer dielectric film provided on the transistor. The first silicon oxide film is provided for preventing etching of the interlayer dielectric film. Subsequently, an amorphous silicon film is deposited on the first silicon oxide film. The silicon film is used to form the storage node and has density lower than density of the first silicon oxide film. Following this, a second silicon oxide is deposited on the silicon film. The second silicon oxide film is used to shape said silicon film. The second silicon oxide film is selectively removed after the silicon film is shaped using the second silicon oxide.

REFERENCES:
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5447878 (1995-09-01), Park et al.
patent: 5550077 (1996-08-01), Tseng et al.
patent: 5659351 (1997-08-01), Wu
T. Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM 88, 1998, pp. 592-595.

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