Methods for making compact P-channel/N-channel transistor struct

Details Methods for making compact P-channel/N-channel transistor struct Methods for making compact P-channel/N-channel transistor struct

1996-09-13

1999-09-14

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438297, 438226, 438227, 438440, 438442, 438423, H01L 218238

Patent

active

059536047

ABSTRACT:
A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another. The buried dielectric region underlies the two drain regions and contacts portions of both drain regions so as to (a) isolate the first drain region from the second body region and (b) isolate the second drain region from the first body region. The transistor structure can be fabricated according to processes in which formation of the body regions is initiated before or after the dielectric region is formed.

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"Self-aligned Quasi-Semiconductor-On-Insulator CMOS Structure", IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989.

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