Method of making EPROM cell array using n-tank as common source

Details Method of making EPROM cell array using n-tank as common source Method of making EPROM cell array using n-tank as common source

1996-11-20

1999-01-12

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438262, 438528, H01L 218247

Patent

active

058588396

ABSTRACT:
This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation. Therefore, there is no need for wordline (15) decoding of large arrays. In addition to the above features, use of the cell array of this invention saves space by eliminating, in certain types of prior-art arrays, the need for space-consuming columnar metal source lines. In that same type of array, a self-aligned-source etch step and a self-aligned-source implant step are eliminated.

REFERENCES:
patent: 5019527 (1991-05-01), Ohshima et al.
patent: 5350706 (1994-09-01), McElroy et al.
patent: 5411908 (1995-05-01), Santin et al.

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