Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-11-22
1996-07-02
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518908, 36518911, 365193, 365194, 365227, 365228, 365233, 326 28, 326 57, G11C 700
Patent
active
055329616
ABSTRACT:
A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.
REFERENCES:
patent: 5058066 (1991-10-01), Yu
patent: 5210715 (1993-05-01), Houston
patent: 5457659 (1995-10-01), Schaefer
Hayashikoshi Masanori
Mori Shigeru
Suzuki Tomio
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
Tran Andrew Q.
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