Semiconductor memory device with page and nibble modes

Details Semiconductor memory device with page and nibble modes Semiconductor memory device with page and nibble modes

1986-11-24

1988-12-06

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 700, G11C 1140, G11C 800

Patent

active

047899662

ABSTRACT:
In a semiconductor memory device comprising a memory cell array and array control circuit for controlling the memory cell array and being operable in a page mode or a nibble mode, a mode selection circuit is provided for selective connection for operation in the page mode or for operation in the nibble mode. The mode selection circuit of the invention comprises fuse means which can be blown or left unblown for the selective connection.

REFERENCES:
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4238839 (1980-12-01), Redfern et al.
patent: 4446534 (1984-05-01), Smith
patent: 4586167 (1986-04-01), Fujishima et al.
patent: 4675850 (1987-06-01), Kumanoya et al.
Fujishima et al., A 256K Dynamic RAM with Page-Nibble Mode, IEEE Journal of Solid State Circuits vol. SC-18, No. 5, Oct. 1983.
Mohsen et al., "The Design and Performance of CMOS 256K Bit DRAM Devices", SC-19, IEE J. Solid-State Circuits, pp. 610-618 (1984) .

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