System and method for selectively controlling fetching and prefe

Details System and method for selectively controlling fetching and prefe System and method for selectively controlling fetching and prefe

1995-11-06

2000-07-04

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711213, 711122, 712207, 712237, G06F 938, G06F 1200

Patent

active

060852917

ABSTRACT:
Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.

REFERENCES:
patent: 5170476 (1992-12-01), Laakso et al.
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5317718 (1994-05-01), Jouppi
patent: 5357618 (1994-10-01), Mirza et al.
patent: 5361391 (1994-11-01), Westberg
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5388247 (1995-02-01), Goodwin et al.
patent: 5490113 (1996-02-01), Tatosian et al.
patent: 5499335 (1996-03-01), Krishnamohan et al.
patent: 5499355 (1996-03-01), Krishnamohan et al.
patent: 5537573 (1996-07-01), Ware et al.
patent: 5627993 (1997-05-01), Abato et al.
patent: 5664147 (1997-09-01), Mayfield
patent: 5761706 (1998-06-01), Kessler et al.
patent: 5784711 (1998-07-01), Chi
Dahlgren and Stenstrom, "Effective Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors", High Performance Computer Architecture, 1995 Symposium pp 68-77.
Tien-Fu Chen, "Effective hardware-based data prefetching for high-performance", IEEE Transaction on Computers, May 1995, vol. 44, Issue 5.
Farkas, K. I. et al., "How useful are non-blocking loads stream buffers and speculative execution in multiple issue processors?", High-Performance Computer Architecture, 1995, Proceedings., First IEEE Symposium, pp 78-89, Jan. 22-25, 1995.
Patterson, D. A., et al., "Computer Organization & Design the Hardware/Software Interface", Morgan Kaufmann. Publishers, Inc., pp 520-521, 1994.
Palacharla, S., et al., "Evaluating Stream Buffers as a Secondary Cache Replacement," 1994 IEEE 1063-6897/94, pp. 24-33.

Affiliated with

Also associated with

Rating

System and method for selectively controlling fetching and prefe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for selectively controlling fetching and prefe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for selectively controlling fetching and prefe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1496178