Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1997-10-06
2000-07-04
Whitehead, Jr., Carl
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257635, 257649, H01L 2348
Patent
active
060843055
ABSTRACT:
A semiconductor device structure and method for producing a shaped etch-front during an etching process. In one embodiment, the present invention is comprised of a first layer of material which is disposed above a contact layer. In this embodiment, the first layer of material has a first etch rate. Next, the present invention deposits a second layer of material above at least a portion of the first layer of material. The second layer of material has a second etch rate which is faster than the first etch rate. Additionally, in the present invention, the first layer of material and the second layer of material have a sloped interfacial topography. The sloped interfacial topography of the present invention creates shaped etch-front during the etching of an opening extending through the first layer of material and the second layer of material. In so doing, the present invention enhances process margin by preventing unwanted etching of portions of the semiconductor device structure during the etching of the opening.
REFERENCES:
patent: Re33622 (1991-06-01), Lee et al.
patent: 4342617 (1982-08-01), Fu et al.
patent: 4807016 (1989-02-01), Douglas
patent: 4814041 (1989-03-01), Auda
patent: 5562801 (1996-10-01), Nulty
patent: 5883436 (1999-03-01), Sadjadi et al.
Jr. Carl Whitehead
Potter Roy
VLSI Technology Inc.
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