Method of fabricating FET device with double spacer

Details Method of fabricating FET device with double spacer Method of fabricating FET device with double spacer

1996-04-25

1997-06-24

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, H01L 21265

Patent

active

056416989

ABSTRACT:
An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 5073514 (1991-12-01), Ito et al.
patent: 5089432 (1992-02-01), Yoo
patent: 5091763 (1992-02-01), Sanchez
patent: 5108939 (1992-04-01), Manley et al.
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5200352 (1993-04-01), Pfiester

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