Self-passivation of copper damascene

Details Self-passivation of copper damascene Self-passivation of copper damascene

1998-07-24

2000-07-04

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438692, 438618, 438622, 438674, 438675, 438680, H01L 2144

Patent

active

060838353

ABSTRACT:
A process for forming damascene wiring within an integrated circuit is described. After the trenches have been filled and planarized, normal dishing of the copper is present. This is then eliminated by depositing a layer of a chrome-copper alloy over the damascene wiring and then planarizing this layer so that it covers only the copper in the damascene trench. Then, while the IMD is deposited, some of the chromium in the alloy gets selectively oxidized, resulting in a self-aligned barrier layer of chromium oxide at the copper to IMD interface.

REFERENCES:
patent: 5173442 (1992-12-01), Carey
patent: 5380546 (1995-01-01), Krishnan et al.
patent: 5451551 (1995-09-01), Krishnan et al.
patent: 6004188 (1999-12-01), Roy

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