Method to perform selective drain engineering with a non-critica

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438302, 438525, H01L 21336

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active

060837942

ABSTRACT:
A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

REFERENCES:
patent: Re35036 (1995-09-01), Yabu et al.
patent: 4232439 (1980-11-01), Shibata
patent: 5188975 (1993-02-01), Kojima et al.
patent: 5190887 (1993-03-01), Tang et al.
patent: 5198384 (1993-03-01), Dennison
patent: 5240874 (1993-08-01), Roberts
patent: 5344787 (1994-09-01), Nagalingam et al.
patent: 5346841 (1994-09-01), Yajima
patent: 5355006 (1994-10-01), Iguchi
patent: 5382540 (1995-01-01), Sharma et al.
patent: 5386131 (1995-01-01), Sato
patent: 5416349 (1995-05-01), Bergemont
patent: 5429960 (1995-07-01), Hong
patent: 5432107 (1995-07-01), Uno et al.
patent: 5441910 (1995-08-01), Nakashiba
patent: 5705410 (1998-01-01), Guegan
patent: 5770502 (1998-06-01), Lee
patent: 5783457 (1999-07-01), Hsu
patent: 5851886 (1998-12-01), Peng
patent: 5891774 (1999-04-01), Ueda et al.
patent: 5915185 (1999-06-01), Fratin et al.
patent: 5920776 (1999-07-01), Fratin et al.
Electronics and Communications in Japan, Part 2, vol. 73, No. 3, 1990 "Improvement of Asymmetrical Characteristics in Submicron CMOS Devices".
IEEE CAT., No. 88 CH-2597-3, 1988 Symposium of VLSI Technology Digest of Technical Papers, May 10-13, 1988, A New Submicron MOSFET with LATID (Large Tilt-Angle Implanted Drain) Structure.

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