Self-aligned stacked gate etch process for fabricating a two-tra

Details Self-aligned stacked gate etch process for fabricating a two-tra Self-aligned stacked gate etch process for fabricating a two-tra

1997-12-15

2000-07-04

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438257, 438241, H01L 21336

Patent

active

060837918

ABSTRACT:
A process for fabricating a two-transistor EEPROM cell that includes a self-aligned stack gate etch step. In the self-aligned stack gate etch step, poly 2 word lines are used as a self-aligned mask to define edges of a poly 1 floating gate that are parallel to the edges of the poly 2 word line, and a patterned photoresist layer is used to define poly 1 access transistor lines. The process provides for employing a self-aligned stacked gate etch without risk of silicon substrate trenching. The process also provides for the fabrication of two-transistor EEPROM cell arrays of high packing density since the need for misalignment driven poly 2 overlap of poly 1 is eliminated.

REFERENCES:
patent: 5240870 (1993-08-01), Bergemont
patent: 5371030 (1994-12-01), Bergemont
Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, pp. 628-635, 1990.

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