Method of forming a source implant at a contact masking step of

Details Method of forming a source implant at a contact masking step of Method of forming a source implant at a contact masking step of

1997-03-07

1998-12-15

Graybill, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438230, 438305, 438307, H01L 21336

Patent

active

058496220

ABSTRACT:
In the fabrication of an integrated circuit having both N MOSFETs and P MOSFETs in which the respective N-type species and P-type species have substantially different diffusivities, the source implant of the dopant species having a the higher diffusivity is advantageously delayed until a contact masking process step. By delaying the dopant species having the higher diffusivity, depletion of the dopant by subsequent annealing steps is avoided. P MOSFETs formed using a high diffusivity boron implant species in an integrated circuit including both P MOSFETs and N MOSFET are fabricated with no source implant in the source regions during formation of the gate electrodes and sidewall spaces. Once the gate and spacer structures on the surface of a substrate wafer are complete and a contact masking step is performed for patterning contact vias, typically in preparation for contact metallization, contact vias are cut to the surface of the substrate and the substrate in the source area exposed by the vias is implanted with the source dopant. A method of fabricating an integrated circuit includes forming a lightly-doped drain(LDD) MOSFET structure prior to source/drain doping. The LDD MOSFET structure includes a gate formed on a substrate over a gate oxide layer, spacers formed on sides of the gate, LDD doping of the substrate in a source region and a drain region self-aligned with the gate. The method further includes forming an oxide layer over the substrate and LDD MOSFET structure, cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate, and implanting a source implant through the contact via into the source of the LDD MOSFET structure.

REFERENCES:
patent: 5547885 (1996-08-01), Ogoh
patent: 5547888 (1996-08-01), Yamazaki
patent: 5578509 (1996-11-01), Fujita
patent: 5602055 (1997-02-01), Nicholls et al.
patent: 5607869 (1997-03-01), Yamazaki
patent: 5654215 (1997-08-01), Gardner et al.
patent: 5656518 (1997-08-01), Gardner et al.

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