Method of making stacked gate memory cell structure

Details Method of making stacked gate memory cell structure Method of making stacked gate memory cell structure

1997-11-20

1999-11-09

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, H01L 218247, H01L 218242

Patent

active

059813350

ABSTRACT:
A stacked gate memory cell having a retention time approaching that of an EEPROM cell and a program and erase time approaching that of a DRAM cell is disclosed. A stacked gate memory cell is fabricated upon a semiconductor substrate by implanting a deep diffusion well in the semiconductor substrate. Next a second diffusion well is implanted in the deep diffusion well. A MOS transistor is formed by implanting a drain diffusion and a source diffusion in the second diffusion well at a channel length apart. The source will be strapped to the second diffusion well. A tunnel oxide is placed on a top surface of the semiconductor substrate in a channel area between the source and drain. A polysilicon gate electrode is placed on the tunnel oxide above the channel area. An insulating layer is then placed on the surface of the semiconductor substrate. A stacked capacitor is formed above the MOS transistor on the surface of the insulating layer. The stacked capacitor has a polysilicon first plate insulating layer and connected by a shorting plug to the gate electrode through an opening in the insulating layer. The gate electrode and the first plate will form a floating gate for the MOS transistor. A capacitor dielectric placed upon the first plate; and a polysilicon second plate on the capacitor dielectric. The second plate will form a control gate for the MOS transistor.

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B. El Kareh et al, "The Evolution of DRAM Cell Technology", Solid State Technology, May 1997, pp. 89-101.

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