Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-12
1999-11-09
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
257369, 438201, H01L 218238
Patent
active
059813202
ABSTRACT:
A method of fabricating a CMOSFET includes the steps of selectively forming first and second conductive type wells in a semiconductor substrate, forming an isolation insulating layer at interface of the first and second conductive type wells, forming a first gate electrode formed of a first conductive type electrode over a predetermined area of the second conductive type well and a second gate electrode successively formed of a second conductive type electrode, a diffusion preventing layer, and the first conductive type electrode over a predetermined area of the first conductive type well, forming sidewall spacers on both sides of each of the first and second gate electrodes, forming second and first conductive type impurity regions under surfaces of the first and second conductive type wells, respectively, at both sides of the first and second gate electrodes and the their sidewall spacers, and forming a silicide layer on the first and second gate electrodes and on the semiconductor substrate where the first and second conductive type impurity regions are.
REFERENCES:
patent: 5830789 (1996-11-01), Lien et al.
Tetsuo Hosoya et al., "A Polycide Gate Electrode with a Conductive Diffusion Barrier Formed with ECR Nitrogen Plasma for Dual Gate CMOS ", IEEE Transactions on Electron Devices, vol. 42, No, 12, Dec. 1995, pp. 2111-2116.
Chaudhari Chandra
Hawranek Scott J.
LG Semicon Co. Ltd.
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