Method for making dynamic random access memory cells having doub

Details Method for making dynamic random access memory cells having doub Method for making dynamic random access memory cells having doub

1997-11-05

1998-12-29

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

058541055

ABSTRACT:
An array of DRAM cells having double-crown capacitors with a center post to increase capacitance is achieved. A planar insulating layer is formed over FETs in an array of cells. Node contact openings are etched to each FET. A first polysilicon layer is deposited to fill the node contact openings and provide a polysilicon planar surface. A thick insulating layer is deposited on the first polysilicon layer, and patterned leaving portions having essentially vertical sidewalls over the contact openings. A conformal second polysilicon layer is deposited and etched back to form first polysilicon spacers and the thick insulating layer is removed. A conformal doped silicon oxide layer is deposited over the first polysilicon spacers and etched back to form inner and outer insulating sidewall spacers. A third polysilicon layer is deposited sufficiently thick to fill the opening between the inner insulating sidewall spacers, and the third and first polysilicon layers are etched back to form second polysilicon spacers on the outer insulating sidewall spacers, and a center post between the inner insulating spacers to form the capacitor bottom electrodes. The insulating spacers are removed and a capacitor dielectric layer and a fourth polysilicon layer are deposited to form the top electrodes to complete the double-crown capacitor having a center post.

REFERENCES:
patent: 5399518 (1995-03-01), Sim et al.
patent: 5443993 (1995-08-01), Park et al.
patent: 5491103 (1996-02-01), Ahn et al.
patent: 5508222 (1996-04-01), Sakao
patent: 5545582 (1996-08-01), Roh
patent: 5700709 (1997-12-01), Park et al.

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