Method and apparatus for invalidating a cache while in a low pow

Details Method and apparatus for invalidating a cache while in a low pow Method and apparatus for invalidating a cache while in a low pow

1995-10-16

1997-05-13

Harvey, Jack B.

395468, G06F 132

Patent

active

056301464

ABSTRACT:
A method and apparatus for allowing a processor to invalidate an individual line of its internal cache while in a non-clocked low power state. The present invention includes circuitry for placing the processor in a reduced power consumption state. The present invention also includes circuitry for powering up the processor out of the reduced power consumption state to invalidate data in the cache in order to maintain cache coherency while in the reduced power consumption state.

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