Method of forming a junction in a flash EEPROM cell by tilt angl

Details Method of forming a junction in a flash EEPROM cell by tilt angl Method of forming a junction in a flash EEPROM cell by tilt angl

1996-05-31

1998-06-23

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, H01L 218247

Patent

active

057705020

ABSTRACT:
The present invention forms a modified DDD junction structure in which a DDD structure is formed on stack gate structure side on which a floating gate and a control gate are laminated and a non-DDD structure is formed on split gate side, by forming a first impurity region through a tilt angle implanting of impurity ions at a high level of energy and then forming a second impurity region through a tilt angle implanting of impurity ions at a low level of of energy using a spacer.

REFERENCES:
patent: 5021848 (1991-06-01), Chiu
patent: 5190887 (1993-03-01), Tang et al.
patent: 5413946 (1995-05-01), Hong
patent: 5432109 (1995-07-01), Yamada

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