Method of making NMOS and PMOS devices with simultaneously forme

Details Method of making NMOS and PMOS devices with simultaneously forme Method of making NMOS and PMOS devices with simultaneously forme

1997-02-25

1998-06-23

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, H01L 218238

Patent

active

057704937

ABSTRACT:
A method of making NMOS and PMOS devices with different gate lengths is disclosed. The method includes providing a semiconductor substrate with first and second active regions, forming a gate material over the first and second active regions, forming a photoresist layer over the gate material, irradiating the photoresist layer with a first image pattern over the first active region wherein the first image pattern has a first radiation energy per unit area of the photoresist layer, irradiating the photoresist layer with a second image pattern over the second active region wherein the second image pattern has a second radiation energy per unit area of the photoresist layer, and etching the gate material to simultaneously form a first gate over the first active region and a second gate over the second active region. Preferably, the first and second gates have different lengths due to the first and second image patterns having different exposure times. The invention is well-suited for adjusting the drive current ratio of NMOS and PMOS devices in a CMOS inverter circuit.

REFERENCES:
U.S. Patent Application Serial No. 08/623,802, filed Mar. 29, 1996, entitled "Method of Processing a Semiconductor Wafer for Controlling Drive Current", by Fulford, Jr. et al (copy not enclosed).

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