Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-18
1998-06-23
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438933, 438165, 438168, 438216, 438249, 438291, H01L 218238
Patent
active
057704929
ABSTRACT:
A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer. The germanium-silicon alloy masks the first set of doped wells against subsequent etching and an ion implantation step that forms the second set of doped wells. Since the locations at which the germanium-silicon alloy deposits are defined by the locations of the first set of wells, the second set of wells is automatically aligned with respect to the first set of wells and about 500 .ANG. thick.
REFERENCES:
patent: 3879619 (1975-04-01), Pleshko
patent: 4373253 (1983-02-01), Khadder et al.
patent: 4523111 (1985-06-01), Baliga
patent: 4527325 (1985-07-01), Geipel et al.
patent: 4558508 (1985-12-01), Kinney
patent: 4568842 (1986-02-01), Koike
patent: 4654548 (1987-03-01), Tanizawa et al.
patent: 4786958 (1988-11-01), Bhagat
patent: 4816705 (1989-03-01), Ohba et al.
patent: 4947064 (1990-08-01), Kim et al.
patent: 5132241 (1992-07-01), Su
patent: 5160855 (1992-11-01), Dobberpahl
patent: 5216294 (1993-06-01), Ryu
patent: 5252501 (1993-10-01), Moslehi
patent: 5266849 (1993-11-01), Kitahara et al.
patent: 5324683 (1994-06-01), Fitch et al.
VLSI Fabrication Principles, Silicon and Gallium Arsenide, Sorab K. Ghandhi, Rensselaer Polytechnic Institute, John Wiley & Sons, 1983, pp. 392-394.
LSI Logic Corporation
Niebling John
Pham Long
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