Static type semiconductor memory with multi-stage sense amplifie

Details Static type semiconductor memory with multi-stage sense amplifie Static type semiconductor memory with multi-stage sense amplifie

1988-07-06

1990-01-02

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365207, 365190, 365202, 307530, G11C 700

Patent

active

048917923

ABSTRACT:
Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

REFERENCES:
patent: 4777625 (1988-10-01), Sakui et al.
patent: 4780850 (1988-10-01), Miyamoto et al.
patent: 4791616 (1988-12-01), Taguchi et al.

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