Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-06-19
1999-06-29
Codd, Bernard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438307, 438589, 438754, 438756, 438757, 430312, 430314, 430317, 430319, H01L 21266
Patent
active
059181346
ABSTRACT:
A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of the dielectric layer having a lateral dimension approximately equal to the minimum feature size resolvable by the photolithography exposure device. The exposed region of the dielectric layer is then removed to form a trench in the dielectric layer having opposed dielectric sidewalls and to expose a channel region of the semiconductor substrate having a lateral dimension approximately equal to the minimum feature size. First and second spacer structures are then formed on the respective dielectric sidewalls. The spacer structures shadow peripheral portions of the exposed channel region. A channel dielectric is then formed between the first and second spacer structures. An outer surface of the spacer structure is then removed to expose peripheral portions of the channel region. A first concentration of a first impurity is then introduced into the peripheral portions of the semiconductor substrate and the channel dielectric is thereafter removed. A gate dielectric is then formed on the semiconductor substrate and a conductive gate structure, such as polysilicon, is formed over the gate dielectric.
REFERENCES:
patent: 3764423 (1973-10-01), Hauser et al.
patent: 4471524 (1984-09-01), Kinsbron et al.
patent: 5270234 (1993-12-01), Huang et al.
patent: 5448094 (1995-09-01), Hsu
patent: 5512517 (1996-04-01), Bryant
patent: 5534456 (1996-07-01), Yuan et al.
patent: 5552329 (1996-09-01), Kim et al.
International Search Report for PCT/US 97 02491 dated Jun. 20, 1997.
Fulford Jr. H. Jim
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Codd Bernard
Daffer Kevin L.
LandOfFree
Method of reducing transistor channel length with oxidation inhi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing transistor channel length with oxidation inhi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing transistor channel length with oxidation inhi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1386452