Method of manufacture of pull down transistor with drain off-set

Details Method of manufacture of pull down transistor with drain off-set Method of manufacture of pull down transistor with drain off-set

1995-07-17

1997-05-13

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438238, H01L 21265

Patent

active

056292201

ABSTRACT:
The pull down transistor of a static SRAM semiconductor device is formed with oxide and polysilicon regions formed on a doped silicon substrate. A masking area is formed over the drain side of the polysilicon and the areas of the drain region proximal to the gate structure in the silicon and oxide layers below. N+ dopant is implanted into the unmasked areas of said substrate about the polysilicon region with the drain doping offset by the resist overlying the proximal portion of the drain region. A spacer is formed by chemical vapor deposition about the polysilicon region. Next an N- implantation follows with the offset provided by the spacers about the polysilicon region.

REFERENCES:
patent: 4318216 (1982-03-01), Hsu
patent: 4795719 (1989-01-01), Eitan
patent: 4837173 (1989-06-01), Alvis et al.
patent: 5091763 (1992-02-01), Sanchez
patent: 5210044 (1993-05-01), Yoshikawa
patent: 5268318 (1993-12-01), Harari
"A Polysilicon Transistor Technology for Large Capacity SRAMs" by Ikeda et al, IEDM, 1990, pp. 469-472.
"A 23-ns 4-Mb CMOS SRAM with 0.2-.mu.A stand by Current", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1075-1080, by Sasaki et al.
"A 5.9.mu.m.sup.2 Super Low Power SRAM Cell Using a New Phase-Shift Lithography" by Yamanaka et al, IEDM, 1990, pp. 477-480.

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