Method and apparatus for global testing the impedance of a progr

Details Method and apparatus for global testing the impedance of a progr Method and apparatus for global testing the impedance of a progr

1998-06-04

1999-04-06

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652257, G11C 1604, G11C 700

Patent

active

058927166

ABSTRACT:
A unique latch circuitry having both a latching and margin testing capability is provided. Every antifuse in a memory circuit is connected to a respective latch circuit. The latch circuits utilize a global input signal to configure a reference impedance with either a normal operational mode impedance or a test mode impedance. Once configured, and without any other additional circuitry, the latch circuits are capable of performing the latching or testing capability based upon comparisons to the reference impedance. When configured for the normal operational mode, the latch circuits read and output the status of their respective antifuses responsive to a control signal. When configured for the testing mode, the latch circuits test the impedance margin of their respective antifuses responsive to the same control signal. The configuration of the unique latch circuit, and the use of the same control signal for normal and test modes, allows for the global testing of all of the antifuses in a memory circuit while reducing the circuitry required to perform the testing. In addition, it is also possible to have different reference impedances for the normal and test modes.

REFERENCES:
patent: 5680360 (1997-10-01), Pilling et al.
patent: 5689455 (1997-11-01), Mullarkey et al.
patent: 5706238 (1998-01-01), Cutter et al.
patent: 5734617 (1998-03-01), Zheng
patent: 5742555 (1998-04-01), Marr et al.

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