Method of fabricating tetra-state mask read only memory

Details Method of fabricating tetra-state mask read only memory Method of fabricating tetra-state mask read only memory

1998-01-20

1999-04-06

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438278, H01L 218236

Patent

active

058917799

ABSTRACT:
A method of fabricating a tetra-state mask read only memory. A memory device is fabricated. Using a first photo-resist to dope the channel regions, a first coding step is performed to obtain a transistor having two different threshold voltage. Covering a gate oxide layer, and etching the first photo-resist layer to form a via, a buried bit line is formed. A poly-silicon layer is formed on the gate oxide layer. Doping the second poly-silicon layer by implanting ions to the source/drain regions, and using a second photo-resist layer, a second coding step is performed. An inverse transistor with two different threshold voltage is formed.

REFERENCES:
patent: 5358887 (1994-10-01), Hong
patent: 5545580 (1996-08-01), Sheng et al.
patent: 5585297 (1996-12-01), Sheng et al.
patent: 5661326 (1997-08-01), Hong
patent: 5693551 (1997-12-01), Su et al.
patent: 5721169 (1998-02-01), Lee

Affiliated with

Also associated with

Rating

Method of fabricating tetra-state mask read only memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating tetra-state mask read only memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating tetra-state mask read only memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1371055