Method and circuit for error checking and correction in a decodi

Details Method and circuit for error checking and correction in a decodi Method and circuit for error checking and correction in a decodi

1997-12-18

2000-03-28

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714767, 714768, 3652385, G11C 2900

Patent

active

060444843

ABSTRACT:
Memory read circuit and method for reducing the number of the memory read cycles required for ECC. The memory read method for ECC of a data memory, which stores sector data reproduced from a compact disc in a decoding device of a compact disc-ROM drive, includes the step of reading the data memory in a page mode read cycle having a page length which corresponds to a physical address where symbols for ECC are stored at the data memory.

REFERENCES:
patent: 4847705 (1989-07-01), Weng et al.
patent: 4901318 (1990-02-01), Tomisawa
patent: 5077720 (1991-12-01), Takagi et al.
patent: 5455795 (1995-10-01), Nakao et al.
patent: 5500819 (1996-03-01), Runas
patent: 5691943 (1997-11-01), Yun

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