Memory controller with buffered CAS/RAS external synchronization

Details Memory controller with buffered CAS/RAS external synchronization Memory controller with buffered CAS/RAS external synchronization

1997-04-08

2000-03-28

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

713503, G06F 104

Patent

active

060444746

ABSTRACT:
Clock-to-signal skew has largely been accepted and tolerated as a design issue; a memory controller that addresses the issue is described. The memory controller is configurable to operate either in a high-performance mode with external synchronization or in a normal mode. In high-performance mode, the memory controller generates a memory control signal, one clock cycle earlier than it would in normal mode, as input for a register. The register buffers the (early) signal. An external clock signal serves as a synchronization event; that is, the clock signal synchronizes the memory control signal by causing the register to output that signal at a more precisely controlled time than might otherwise occur using the memory controller alone. Thus, the use of the external clock signal helps compensate for the effects of clock-to-signal skew; multiple external synchronization registers may also be used.

REFERENCES:
patent: 4858178 (1989-08-01), Breuninger
patent: 5291580 (1994-03-01), Bowden, III et al.
patent: 5615355 (1997-03-01), Wagner
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5819076 (1998-10-01), Jeddeloh et al.
patent: 5857095 (1999-01-01), Jeddeloh et al.

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