Memory device output circuit having multiple operating modes

Details Memory device output circuit having multiple operating modes Memory device output circuit having multiple operating modes

1999-04-20

1999-11-16

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, 365226, 36523003, G11C 704

Patent

active

059869453

ABSTRACT:
A memory device that includes decoding circuitry, a memory array, conditioning circuitry, and an output circuit. The decoding circuitry is configured to receive address information and generate a set of control signals. The memory array couples to the decoding circuitry and is configured to provide a data value in response to the set of control signals. The conditioning circuitry couples to the memory array and is configured to receive and condition the data value to provide a data bit. The output circuit couples to the conditioning circuitry and is configured to receive the data bit and provide an output bit. The output circuit is further configured to operate in one of a number of operating modes, with each operating mode corresponding to a different timing scheme. The output circuit can be implemented using a pair of latches coupled in series. The different operating modes can be achieved, for example, by selectively placing one of the latches in a bypass mode. A timing circuit can be used to provide the necessary clock signal(s) for the output circuit.

REFERENCES:
patent: 5703811 (1997-12-01), Yoo et al.
patent: 5786711 (1998-07-01), Choi
patent: 5798969 (1998-08-01), Yoo et al.

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