Method and apparatus using a data read latch circuit in a semico

Details Method and apparatus using a data read latch circuit in a semico Method and apparatus using a data read latch circuit in a semico

1998-11-10

1999-11-16

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365205, 365207, 365208, G11C 1604

Patent

active

059869445

ABSTRACT:
A method and circuit for self-latching data read lines that are used to transfer data that is read from a memory array of a memory device to a data output register of the memory device, wherein a self-latching latch circuit is connected to each data read line. The latch circuits are located physically near the output of the memory array, for latching data that is read from the memory array as soon as the data is applied to the data read lines, and prior to the data being latched in the data output register, thereby minimizing the effects of propagation delay so that the memory cycle time can be decreased. In one embodiment wherein the memory is organized in a "x4" configuration, different groups of the data read lines are selected in alternate read cycles, and the data read lines of the non-selected data read group are equilibrated automatically during the read cycle using the conventional test circuits of the memory device.

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"Micron 4 MEG X 4/2 MEG X 8 SDRAM", Micron Synchronous DRAM Data Book, Micron Technology, Inc., 1-44, (Rev. Feb. 1997).

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