Semiconductor device handling multi-level voltages

Details Semiconductor device handling multi-level voltages Semiconductor device handling multi-level voltages

1998-02-02

2000-03-28

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438911, H01L 21336

Patent

active

060431288

ABSTRACT:
A method of fabricating a multi power source semiconductor device handling multi-level voltages, comprises the steps of: forming first gate oxide layers by thermally oxidizing surfaces of the plurality of the active regions of said semiconductor substrate; forming a first mask having a window on a first active region among said plurality of the active regions of said semiconductor substrate; implanting impurity ions for controlling a threshold voltage, into a surface of said first active region through the first mask; removing the first gate oxide layer on the first active region exposed in the window of said first mask; removing said first mask; forming a thin second gate oxide layer on the first active region and a thick third gate oxide layer on a second active region different from the first active region among said plurality of the active regions by further thermally oxidizing the surfaces of the plurality of the active regions; forming on the semiconductor substrate a second mask having a window on the second active region; and implanting impurity ions for controlling a threshold voltage, into a surface of the second active region through said second mask. A method of fabricating a multi power source semiconductor device capable of realizing gate oxide layers of different thickness and different channel doping with a small number of masks is provided.

REFERENCES:
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patent: 4535529 (1985-08-01), Jochems
patent: 4651406 (1987-03-01), Shimizu et al.
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patent: 5607868 (1997-03-01), Chida et al.
patent: 5712201 (1998-01-01), Lee et al.
patent: 5834352 (1998-11-01), Choi

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