Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Patent
1997-09-30
1999-07-20
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
257773, 257784, H01L 23492
Patent
active
059259353
ABSTRACT:
A semiconductor chip comprises a plurality of bonding pads formed in a row along an edge of the chip and spaced at a designated gap pitch between confronting sides of adjacent pads. Each of the pads has a length perpendicular to the edge of the chip, a length distance, a width parallel to the edge of the chip, and a width distance. The length distance is different than the width distance.
REFERENCES:
patent: 5300815 (1994-04-01), Rostoker
patent: 5444303 (1995-08-01), Greenwood et al.
patent: 5569964 (1996-10-01), Ikebe
patent: 5796171 (1998-08-01), Koc et al.
Horner, Rita N. et al., "Implementation of Pad Circuitry for Radially Staggered Bond Pad Arrangements" Hwelett-Packard Journal, Dec. 1996, pp. 51-54.
"Unique Pad Geometry for Optimum Solder Application" IBM Technical Disclosure Bulletin, vol. 34, No. 1, Jun. 1991, pp. 465-466.
Hardy David B.
Samsung Electronics Co,. Ltd.
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