Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-29
1999-11-16
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438 3, 438393, 438250, 438258, 438685, 438643, 438653, 257295, 257763, 257768, 257769, 365145, 365149, H01L 2976, G11C 1122, G11C 1124
Patent
active
059857137
ABSTRACT:
An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.
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Meza, Esq. Peter J.
Nguyen Ha Tran
Niebling John F.
Ramtron International Corporation
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