Method of manufacturing vertical power device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438268, H01L 218249

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active

059857080

ABSTRACT:
A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.

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Keiji Tanaka et al., "Characteristics of Field-Induced-Drain (FID) Poly-Si TFT's with High On/Off Current Ratio", IEEE Transactions On Electron Devices, vol. 39, No. 4, Apr. 1992, pp. 916-919.
G.M. Dolny et al., "Polycrystalline-Silicon Thin-Film Transistor Technology for Low Cost, High-Power Integrated Circuits", IEEE IEDM Technical Digest, Apr. 1992, pp. 233-236.

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