Method for fabrication of a one gigabit capacitor over bit line

Details Method for fabrication of a one gigabit capacitor over bit line Method for fabrication of a one gigabit capacitor over bit line

1998-02-27

1999-03-09

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438672, H01L 218242

Patent

active

058799869

ABSTRACT:
A process for fabricating a high density, capacitor over bit line, DRAM cell, using 8F.sup.2 technology, has been developed. The process features self-alignment of a tungsten bit line structure, to polycide word lines, and self-alignment of a capacitor node structure, to both tungsten bit lines, and to polycide word line structures. Self-alignment is accomplished by opening contact holes between polycide gate structures, and between tungsten bit line structures, which are coated with silicon nitride spacers, followed by filling with polysilicon plugs, which in turn contact underlying regions of the semiconductor substrate.

REFERENCES:
patent: 5100838 (1992-03-01), Dennison
patent: 5330614 (1994-07-01), Ahn
patent: 5688713 (1997-11-01), Linliu et al.

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